----------------------------------------------------------------------------------
-- Company: 
-- tianszzz 
-- 
-- Create Date:    18:34:38 10/23/2021 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity Counter is
    port(
		clk    : in STD_LOGIC;		  	  
		QA     : out STD_LOGIC;
		QB     : out STD_LOGIC;
		QC     : out STD_LOGIC;	
		QD     : out STD_LOGIC;
		rco    : out STD_LOGIC
	 );
	 
end Counter;

ARCHITECTURE Behavioral OF Counter IS
   
	SIGNAL	load_n :  STD_LOGIC;
	SIGNAL	clr_n  :  STD_LOGIC;
	SIGNAL	ent  :  STD_LOGIC;
	SIGNAL	enp  :  STD_LOGIC;
	SIGNAL	A      :  STD_LOGIC;
	SIGNAL	B      :  STD_LOGIC;
	SIGNAL	C      : STD_LOGIC;
	SIGNAL	D      : STD_LOGIC;		  

	
	signal   temp1  :STD_LOGIC;
	signal   temp2  :STD_LOGIC;
	signal   temp3  :STD_LOGIC;
	signal   temp4  :STD_LOGIC;	
	

	component ls161
    Port (
		load_n : in STD_LOGIC;
		clr_n  : in STD_LOGIC;
		clk    : in STD_LOGIC;		  
		ent    : in STD_LOGIC;
		enp    : in STD_LOGIC;
		A      : in STD_LOGIC;
		B      : in STD_LOGIC;
		C      : in STD_LOGIC;
		D      : in STD_LOGIC;		  
		QA     : out STD_LOGIC;
		QB     : out STD_LOGIC;
		QC     : out STD_LOGIC;
		QD     : out STD_LOGIC;	
      rco    : out STD_LOGIC	
		);		
end component; 

BEGIN
	QD <= temp1;
	QB <= temp2;	
u1:ls161 port map(
        load_n => temp2,
        clr_n => '1',		  
        clk => clk,
        ent => '1',
        enp => '1',
        A => '0',
        B => '1',
        C => '1',
        D => temp1,
        QA => QA,
        QB => temp2,
        QC => QC,
        QD => temp1,
        rco => rco
        );
   
END Behavioral;

